Introducing switching regulators Basis of their analysis in steady state Detailed study of the basic DC/DC converters in continuous conduction mode Buck, Boost and Buck-Boost converters Common and different properties Introduction to the synchronous rectification Four-order converters Outline (I)
Study of the basic DC/DC converters in discontinuous conduction mode DC/DC converters with galvanic isolation How and where to place a transformer in a DC/DC converter The Forward and Flyback converters Outline (II)
Linear DC/DC conversion (analog circuitry) First idea ??= (vOiO)/(vgig) iO ? ig ? ? vO/vg (Gp:) Actual implementation (Gp:) – (Gp:) Vref (Gp:) Av (Gp:) Feedback loop (Gp:) vE (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) Q (Gp:) iO (Gp:) ig
Only a few components Robust No EMI generation Only lower output voltage Efficiency depends on input/output voltages Low efficiency Bulky (Gp:) – (Gp:) Vref (Gp:) Av (Gp:) Feedback loop (Gp:) vE (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) RV (Gp:) iO (Gp:) ig
Linear versus switching DC/DC conversion Linear (Gp:) – (Gp:) Vref (Gp:) Av (Gp:) Feedback loop (Gp:) vE (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) Q (Gp:) iO (Gp:) ig
Switching (provisional) (Gp:) – (Gp:) Vref (Gp:) Av (Gp:) Feedback loop (Gp:) vE (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) PWM
(Gp:) vO (Gp:) vg (Gp:) t
Features: 100% efficiency Undesirable output voltage waveform (Gp:) vO_avg
Introducing the switching DC/DC conversion (I) Basic switching DC/DC converter (provisional) (Gp:) – (Gp:) Vref (Gp:) Av (Gp:) Feedback loop (Gp:) vE (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) PWM
(Gp:) vO (Gp:) vg (Gp:) t (Gp:) vO_avg
The AC component must be removed!! (Gp:) – (Gp:) Vref (Gp:) Av (Gp:) Feedback loop (Gp:) vE (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) PWM (Gp:) Filter
(Gp:) VO (Gp:) Vg (Gp:) t
(Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) C filter
(Gp:) C filter
It doesn’t work!!!
Introducing the switching DC/DC conversion (II) Basic switching DC/DC converter (Gp:) vD (Gp:) Vg (Gp:) t (Gp:) VO
(Gp:) – (Gp:) Vref (Gp:) Av (Gp:) Feedback loop (Gp:) vE (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) PWM (Gp:) Filter
(Gp:) LC filter
Infinite voltage across L when S1 is opened It doesn’t work either!!! (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) LC filter (Gp:) iL (Gp:) C (Gp:) L
(Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) LC filter (Gp:) iL (Gp:) C (Gp:) L (Gp:) iD (Gp:) D (Gp:) vD (Gp:) + (Gp:) – (Gp:) + (Gp:) –
(Gp:) Including a diode
Introducing the switching DC/DC conversion (III) Buck converter (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) LC filter (Gp:) iL (Gp:) C (Gp:) L (Gp:) iD (Gp:) D (Gp:) vD (Gp:) + (Gp:) – (Gp:) + (Gp:) –
(Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) iL (Gp:) C (Gp:) L (Gp:) iD (Gp:) D (Gp:) vD (Gp:) + (Gp:) – (Gp:) + (Gp:) – (Gp:) iS
Starting the analysis of the Buck converter in steady state: L & C designed for negligible output voltage ripple (we are designing a DC/DC converter) iL never reaches zero (Continuous Conduction Mode, CCM) The study of the Discontinuous Conduction Mode (DCM) will done later (Gp:) t (Gp:) iL (Gp:) CCM
(Gp:) t (Gp:) iL (Gp:) DCM
First analysis of the Buck converter in CCM (Gp:) – (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) iL (Gp:) C (Gp:) L (Gp:) iD (Gp:) D (Gp:) vD (Gp:) + (Gp:) + (Gp:) – (Gp:) iS
(In steady-state) (Gp:) – (Gp:) RL (Gp:) vO (Gp:) iO (Gp:) iL (Gp:) C (Gp:) L (Gp:) vD (Gp:) + (Gp:) + (Gp:) LC filter
(Gp:) vD (Gp:) vg
(Gp:) t (Gp:) vD_avg
The AC component is removed by the filter Analysis based on the specific topology of the Buck converter = vO vO = vD_avg = d·vg (Gp:) T (Gp:) dT (Gp:) t (Gp:) vD (Gp:) vO (Gp:) vg (Gp:) d: “duty cycle”
This procedure is only valid for converter with explicit LC filter
Introducing another analysis method (I) Obviously, there is not an explicit LC filter Therefore, we must use another method (Gp:) R (Gp:) Vg (Gp:) VO (Gp:) + (Gp:) – (Gp:) ig (Gp:) iS (Gp:) iD (Gp:) L1 (Gp:) C2 (Gp:) S (Gp:) D (Gp:) iL2 (Gp:) L2 (Gp:) C1 (Gp:) + (Gp:) –
(Gp:) Could we use the aforementioned analysis in the case of this converter (SEPIC)?
Introducing another analysis method (II) Powerful tools to analyze DC/DC converters in steady-state Step 1- To obtain the main waveforms (with no quantity values) using Faraday’s law and Kirchhoff’s current and voltage laws Step 2- To take into account the average value of the voltage across inductors and of the current through capacitors in steady-state Step 2 (bis)- To use the volt·second balance Step 3- To apply Kirchhoff’s current and voltage laws in average values Step 4- Input-output power balance
Introducing another analysis method (III) Any electrical circuit that operates in steady-state satisfies: The average voltage across an inductor is zero. Else, the net current through the inductor always increases and, therefore, steady-state is not achieved The average current through a capacitor is zero. Else, the net voltage across the capacitor always increases and, therefore, steady-state is not achieved (Gp:) + (Gp:) – (Gp:) vL_avg = 0
(Gp:) iC_avg = 0
(Gp:) Vg (Gp:) Circuit in steady-state (Gp:) L (Gp:) C
Introducing another analysis method (IV) Particular case of many DC/DC converters in steady-state: Voltage across the inductors are rectangular waveforms Current through the capacitors are triangular waveforms (Gp:) + (Gp:) – (Gp:) vL (Gp:) iC (Gp:) Vg (Gp:) Circuit in steady-state (Gp:) L (Gp:) C (Gp:) vL_avg = 0 (Gp:) iC_avg = 0
(Gp:) T (Gp:) dT (Gp:) vL (Gp:) t (Gp:) – (Gp:) + (Gp:) v1 (Gp:) -v2
(Gp:) t (Gp:) iC (Gp:) – (Gp:) +
Volt·second balance: V1dT – V2(1-d)T = 0 (Gp:) Same areas
(Gp:) Same areas
(Gp:) Vg (Gp:) iL1 (Gp:) iS (Gp:) L1 (Gp:) S (Gp:) L2 (Gp:) C1 (Gp:) + (Gp:) – (Gp:) iC1 (Gp:) vL1 (Gp:) + (Gp:) – (Gp:) vL2 (Gp:) + (Gp:) – (Gp:) vC1 (Gp:) Example
Introducing another analysis method (V) Any electrical circuit of small dimensions (compared with the wavelength associated to the frequency variations) satisfies: Kirchhoff’s current law (KCL) is not only satisfied for instantaneous current values, but also for average current values Kirchhoff’s voltage law (KVL) is not only satisfied for instantaneous voltage values, but also for average voltage values KVL applied to Loop1 yields: vg – vL1 – vC1 – vL2 = 0 vg – vL1_avg – vC1_avg – vL2_avg = 0 Therefore: vC1_avg = vg KCL applied to Node1 yields: iL1 – iC1 – iS = 0 iL1_avg – iC1_avg – iS_avg = 0 Therefore: iS_avg = iL1_avg (Gp:) Loop1
(Gp:) Node1
Introducing another analysis method (VI) A switching converter is (ideally) a lossless system (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) iO (Gp:) ig (Gp:) + (Gp:) – (Gp:) Switching-mode DC/DC converter
Input power: Pg = vgig_avg Output power: PO = vOiO = vO2/RL Power balance: Pg = PO (Gp:) DC Transformer (Gp:) vg (Gp:) iO (Gp:) ig_avg (Gp:) RL (Gp:) vO (Gp:) + (Gp:) – (Gp:) 1:N
A switching-mode DC/DC converter as an ideal DC transformer being N = vO/vg Important concept!! ig_avg = iOvO/vg = N·iO
Therefore: vgig_avg = vO2/RL
Steady-state analysis of the Buck converter in CCM (I) Step 1: Main waveforms. Remember that the output voltage remains constant during a switching cycle if the converter has been properly designed (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) iL (Gp:) C (Gp:) L (Gp:) iD (Gp:) D (Gp:) vD (Gp:) + (Gp:) – (Gp:) + (Gp:) – (Gp:) iS (Gp:) vS (Gp:) + (Gp:) –
(Gp:) iO (Gp:) iL (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) C (Gp:) L (Gp:) + (Gp:) – (Gp:) During dT (Gp:) S on, D off
(Gp:) iO (Gp:) iL (Gp:) RL (Gp:) vO (Gp:) C (Gp:) L (Gp:) + (Gp:) – (Gp:) During (1-d)T (Gp:) S off, D on
(Gp:) t (Gp:) t (Gp:) t (Gp:) t (Gp:) iS (Gp:) iD (Gp:) iL (Gp:) Driving signal
(Gp:) dT
(Gp:) T
Step 1: Main waveforms (cont’) RL vg vO S iO iL C L D vD + – + – vS + – Steady-state analysis of the Buck converter in CCM (II) vL + – (Gp:) dT (Gp:) vg-vO
(Gp:) S off, D on, (1-d)T (Gp:) iO (Gp:) iL (Gp:) RL (Gp:) vO (Gp:) C (Gp:) L (Gp:) + (Gp:) – (Gp:) vL (Gp:) + (Gp:) –
(Gp:) S on, D off, dT (Gp:) iO (Gp:) iL (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) C (Gp:) L (Gp:) + (Gp:) – (Gp:) vL (Gp:) + (Gp:) –
(Gp:) T (Gp:) – vO
(Gp:) Driving signal (Gp:) t (Gp:) t (Gp:) t (Gp:) vL (Gp:) iL (Gp:) iL_avg
(Gp:) DiL
From Faraday’s law: DiL = vO(1-d)T/L
(Gp:) + (Gp:) –
Step 2 and 2 (bis): Average inductor voltage and capacitor current Steady-state analysis of the Buck converter in CCM (III) (Gp:) dT (Gp:) vg-vO (Gp:) T (Gp:) – vO (Gp:) Driving signal (Gp:) t (Gp:) t (Gp:) t (Gp:) vL (Gp:) iL (Gp:) iL_avg
KCL applied to Node1 yields: iL – iC – iO = 0 iL_avg – iC_avg – iO = 0 Therefore: iL_avg = iO = vO/RL Volt·second balance over L: (vg – vO)dT – vO(1-d)T = 0 Therefore: vO = d·vg (always vO < vg) (Gp:) RL (Gp:) vO (Gp:) iO (Gp:) iL (Gp:) C (Gp:) L (Gp:) + (Gp:) – (Gp:) vL (Gp:) + (Gp:) – (Gp:) iC (Gp:) Node1 (Gp:) vg (Gp:) S (Gp:) ig (Gp:) iD (Gp:) D (Gp:) iS
Average value of iC: iC_avg = 0
Step 3: Average KCL and KVL: Step 4: Power balance: ig_avg = iS_avg = iOvO/vg = d·iO
Summary Steady-state analysis of the Buck converter in CCM (IV) (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) iL (Gp:) C (Gp:) L (Gp:) iD (Gp:) D (Gp:) vD (Gp:) + (Gp:) – (Gp:) + (Gp:) – (Gp:) iS (Gp:) vS (Gp:) + (Gp:) –
(Gp:) iO (Gp:) t (Gp:) t (Gp:) t (Gp:) iS (Gp:) iD (Gp:) iL (Gp:) dT (Gp:) T (Gp:) t (Gp:) DiL (Gp:) t (Gp:) Driving signal (Gp:) vD (Gp:) vg
iL_avg = iO = vo/RL vO = d·vg (always vO < vg) ig_avg = iS_avg = d·iO iD_avg = iL_avg – iS_avg = (1-d)·iO DiL = vO(1-d)T/L iL_peak = iL_avg + DiL/2 = iO + vO(1-d)T/(2L) vSmax = vDmax = vg iS_peak = iD_peak = iL_peak
Steady-state analysis of the Boost converter in CCM (I) (Gp:) t (Gp:) t (Gp:) t (Gp:) t (Gp:) iS (Gp:) iD (Gp:) iL (Gp:) Driving signal
(Gp:) dT
(Gp:) T
Can we obtain vO > vg? Þ Boost converter (Gp:) S on, D off, during dT (Gp:) iL (Gp:) vg (Gp:) L (Gp:) vL (Gp:) + (Gp:) –
(Gp:) Step 1: Main waveforms (Gp:) + (Gp:) – (Gp:) C (Gp:) vg (Gp:) iL (Gp:) iS (Gp:) L (Gp:) S (Gp:) iD (Gp:) D (Gp:) RL (Gp:) vO (Gp:) iO (Gp:) + (Gp:) – (Gp:) vL (Gp:) + (Gp:) – (Gp:) ig
(Gp:) S off, D on, during (1-d)T (Gp:) iO (Gp:) iL (Gp:) RL (Gp:) vO (Gp:) C (Gp:) L (Gp:) + (Gp:) – (Gp:) vL (Gp:) + (Gp:) –
(Gp:) DiL
From Faraday’s law: DiL = vgdT/L
Steady-state analysis of the Boost converter in CCM (II) Step 2 and 2 (bis): Average values KCL applied to Node1 yields: iD – iC – iO = 0 iD_avg – iC_avg – iO = 0 Therefore: iD_avg = iL_avg(1-d) = iO = vO/RL Volt·second balance over L: vgdT – (vO – vg)(1-d)T = 0 Therefore: vO = vg/(1-d) (always vO > vg) Average value of iC: iC_avg = 0
Step 3: Average KCL and KVL: Step 4: Power balance: ig_avg = iL_avg = iOvO/vg = iO/(1-d)
(Gp:) + (Gp:) – (Gp:) C (Gp:) vg (Gp:) iL (Gp:) iS (Gp:) L (Gp:) S (Gp:) iD (Gp:) D (Gp:) RL (Gp:) vO (Gp:) iO (Gp:) + (Gp:) – (Gp:) vL (Gp:) + (Gp:) – (Gp:) ig (Gp:) iC (Gp:) Node1
(Gp:) dT (Gp:) vg (Gp:) T (Gp:) Driving signal (Gp:) t (Gp:) t (Gp:) t (Gp:) vL (Gp:) iD (Gp:) iD_avg (Gp:) DiL (Gp:) -(vO-vg)
Steady-state analysis of the Boost converter in CCM (III) Summary (Gp:) iO (Gp:) t (Gp:) t (Gp:) t (Gp:) iS (Gp:) iD (Gp:) iL (Gp:) dT (Gp:) T (Gp:) t (Gp:) DiL (Gp:) t (Gp:) Driving signal (Gp:) vD (Gp:) vO
iL_avg = ig_avg = iO/(1-d) = vo/[RL(1-d)] vO = vg/(1-d) (always vO > vg) iS_avg = d·iL_avg = d·vo/[RL(1-d)] iD_avg = iO DiL = vgdT/L iL_peak = iL_avg + DiL/2 = iL_avg + vgdT/(2L) vSmax = vDmax = vO iS_peak = iD_peak = iL_peak (Gp:) vS (Gp:) + (Gp:) – (Gp:) vD (Gp:) + (Gp:) – (Gp:) C (Gp:) vg (Gp:) iL (Gp:) iS (Gp:) L (Gp:) S (Gp:) iD (Gp:) D (Gp:) RL (Gp:) vO (Gp:) iO (Gp:) + (Gp:) – (Gp:) vL (Gp:) + (Gp:) – (Gp:) ig (Gp:) iC
Steady-state analysis of the Buck-Boost converter in CCM (I) (Gp:) t (Gp:) t (Gp:) t (Gp:) t (Gp:) iS (Gp:) iD (Gp:) iL (Gp:) Driving signal
(Gp:) dT
(Gp:) T
Can we obtain either vO < vg or vO > vg? Þ Buck-Boost converter (Gp:) DiL
From Faraday’s law: DiL = vgdT/L (Gp:) + (Gp:) – (Gp:) C (Gp:) D (Gp:) vg (Gp:) iL (Gp:) iS (Gp:) L (Gp:) S (Gp:) iD (Gp:) RL (Gp:) iO (Gp:) vO (Gp:) – (Gp:) + (Gp:) ig (Gp:) vL (Gp:) + (Gp:) –
(Gp:) S on, D off, during dT (Gp:) Charging stage (Gp:) iL (Gp:) vg (Gp:) L (Gp:) vL (Gp:) + (Gp:) – (Gp:) ig
(Gp:) S off, D on, during (1-d)T (Gp:) iO (Gp:) RL (Gp:) vO (Gp:) C (Gp:) – (Gp:) + (Gp:) iL (Gp:) L (Gp:) vL (Gp:) + (Gp:) – (Gp:) Discharging stage (Gp:) + (Gp:) –
Steady-state analysis of the Buck-Boost converter in CCM (II) Step 2 and 2 (bis): Average values KCL applied to Node1 yields: iD – iC – iO = 0 iD_avg – iC_avg – iO = 0 Therefore: iD_avg = iL_avg(1-d) = iO = vO/RL Volt·second balance over L: vgdT – vO(1-d)T = 0 Therefore: vO = vgd/(1-d) Average value of iC: iC_avg = 0 Step 3: Average KCL and KVL: Step 4: Power balance: ig_avg = iS_avg = iOvO/vg = iOd/(1-d) (Gp:) Node1 (Gp:) + (Gp:) – (Gp:) C (Gp:) D (Gp:) vg (Gp:) iL (Gp:) iS (Gp:) L (Gp:) S (Gp:) iD (Gp:) RL (Gp:) iO (Gp:) vO (Gp:) – (Gp:) + (Gp:) ig (Gp:) vL (Gp:) + (Gp:) – (Gp:) iC
(Gp:) dT (Gp:) vg (Gp:) T (Gp:) Driving signal (Gp:) t (Gp:) t (Gp:) t (Gp:) vL (Gp:) iD (Gp:) iD_avg (Gp:) DiL (Gp:) -vO
Steady-state analysis of the Buck-Boost converter in CCM (III) Summary iL_avg = iD_avg/(1-d) = iO/(1-d) = vo/[RL(1-d)] vO = vgd/(1-d) (both vO < vg and vO > vg) iS_avg = ig_avg = d·iL_avg = d·vo/[RL(1-d)] iD_avg = iO DiL = vgdT/L iL_peak = iL_avg + DiL/2 = iL_avg + vgdT/(2L) vSmax = vDmax = vO + vg iS_peak = iD_peak = iL_peak (Gp:) iO (Gp:) t (Gp:) t (Gp:) t (Gp:) iS (Gp:) iD (Gp:) iL (Gp:) dT (Gp:) T (Gp:) t (Gp:) DiL (Gp:) t (Gp:) Driving signal (Gp:) vD (Gp:) vO + vg
(Gp:) + (Gp:) – (Gp:) C (Gp:) D (Gp:) vg (Gp:) iL (Gp:) iS (Gp:) L (Gp:) S (Gp:) iD (Gp:) RL (Gp:) iO (Gp:) vO (Gp:) – (Gp:) + (Gp:) ig (Gp:) vL (Gp:) + (Gp:) – (Gp:) vD (Gp:) – (Gp:) + (Gp:) vS (Gp:) – (Gp:) +
Common issues in basic DC/DC converters (I) (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) C (Gp:) L (Gp:) D (Gp:) + (Gp:) – (Gp:) + (Gp:) – (Gp:) Buck
(Gp:) + (Gp:) – (Gp:) C (Gp:) vg (Gp:) L (Gp:) S (Gp:) D (Gp:) RL (Gp:) vO (Gp:) + (Gp:) – (Gp:) Boost
(Gp:) + (Gp:) – (Gp:) C (Gp:) D (Gp:) vg (Gp:) L (Gp:) S (Gp:) RL (Gp:) vO (Gp:) + (Gp:) – (Gp:) Buck-Boost
(Gp:) Complementary switches + inductor (Gp:) vg (Gp:) RL (Gp:) vO (Gp:) + (Gp:) – (Gp:) + (Gp:) – (Gp:) C (Gp:) L (Gp:) D (Gp:) S (Gp:) d (Gp:) 1-d
(Gp:) Voltage source
The inductor is a energy buffer to connect two voltage sources
Common issues in basic DC/DC converters (II) (Gp:) + (Gp:) – (Gp:) C (Gp:) vg (Gp:) L (Gp:) S (Gp:) D (Gp:) RL (Gp:) vO (Gp:) + (Gp:) – (Gp:) Boost (Gp:) vO
(Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) C (Gp:) L (Gp:) D (Gp:) + (Gp:) – (Gp:) + (Gp:) – (Gp:) Buck (Gp:) vg
(Gp:) + (Gp:) – (Gp:) C (Gp:) D (Gp:) vg (Gp:) L (Gp:) S (Gp:) RL (Gp:) vO (Gp:) + (Gp:) – (Gp:) Buck-Boost (Gp:) vO + vg
Diode turn-off The diode turns off when the transistor turns on The diode reverse recovery time is of primary concern evaluating switching losses Schottky diodes are desired from this point of view In the range of line voltages, SiC diodes are very appreciated
Comparing basic DC/DC converters (I) Generalized study as DC transformer (I) (Gp:) DC Transformer (Gp:) vg (Gp:) iO (Gp:) ig_avg (Gp:) RL (Gp:) vO (Gp:) + (Gp:) – (Gp:) 1:N
(Gp:) + (Gp:) – (Gp:) C (Gp:) vg (Gp:) L (Gp:) S (Gp:) D (Gp:) RL (Gp:) vO (Gp:) iO (Gp:) + (Gp:) – (Gp:) ig (Gp:) Boost
(Gp:) + (Gp:) – (Gp:) C (Gp:) D (Gp:) vg (Gp:) L (Gp:) S (Gp:) RL (Gp:) iO (Gp:) vO (Gp:) + (Gp:) – (Gp:) ig (Gp:) Buck-Boost
(Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iO (Gp:) ig (Gp:) C (Gp:) L (Gp:) D (Gp:) + (Gp:) – (Gp:) + (Gp:) – (Gp:) Buck
Buck: N= d (only vO < vg) Boost: N= 1/(1-d) (only vO > vg) Buck-Boost: N= -d/(1-d) (both vO < vg and vO > vg)
Comparing basic DC/DC converters (II) Generalized study as DC transformer (II) Buck: ig_avg = iON = iOd Boost: ig_avg = iON = iO/(1-d) Buck-Boost: ig_avg = iON = – iOd/(1-d) (Gp:) DC Transformer (Gp:) vg (Gp:) iO (Gp:) ig_avg (Gp:) RL (Gp:) vO (Gp:) + (Gp:) – (Gp:) 1:N (Gp:) ig_avg = iON = iOd/(1-d)
Comparing basic DC/DC converters (III) Electrical stress on components (I) Buck: vSmax = vDmax = vg iS_avg = ig_avg iL_avg = iO iD_avg = iL_avg – iS_avg (Gp:) vg (Gp:) ig (Gp:) iD (Gp:) D (Gp:) vD (Gp:) + (Gp:) – (Gp:) S (Gp:) iS (Gp:) vS (Gp:) + (Gp:) – (Gp:) RL (Gp:) vO (Gp:) iO (Gp:) + (Gp:) – (Gp:) DC/DC converter
Boost: vSmax = vDmax = vO iL_avg = ig_avg iD_avg = iO iS_avg = iL_avg – iD_avg Buck-Boost: vSmax = vDmax = vO + vg iS_avg = ig_avg iD_avg = iO iL_avg = iS_avg + iD_avg
Comparing basic DC/DC converters (IV) Example of electrical stress on components (I) vS_max = vD_max = 100 V iS_avg = iD_avg = 1 A iL_avg = 2 A FOMVA_S = FOMVA_D = 100 VA (Gp:) RL (Gp:) S (Gp:) C (Gp:) L (Gp:) D (Gp:) + (Gp:) – (Gp:) + (Gp:) – (Gp:) 50 V (Gp:) 100 V (Gp:) 2 A (Gp:) 1 A (avg) (Gp:) 100 W Buck, 100% efficiency
(Gp:) + (Gp:) – (Gp:) C (Gp:) D (Gp:) L (Gp:) S (Gp:) RL (Gp:) – (Gp:) + (Gp:) 50 V (Gp:) 100 V (Gp:) 2 A (Gp:) 1 A (avg) (Gp:) 100 W Buck-Boost, 100% efficiency
vS_max = vD_max = 150 V iS_avg = 1 A iD_avg = 2 A iL_avg = 3 A FOMVA_S = 150 VA FOMVA_D = 300 VA Higher electrical stress in the case of Buck-Boost converter Therefore, lower actual efficiency
Comparing basic DC/DC converters (V) Example of electrical stress on components (II) vS_max = vD_max = 50 V iS_avg = iD_avg = 2 A iL_avg = 4 A FOMVA_S = FOMVA_D = 100 VA (Gp:) + (Gp:) – (Gp:) C (Gp:) L (Gp:) S (Gp:) D (Gp:) RL (Gp:) + (Gp:) – (Gp:) 50 V (Gp:) 25 V (Gp:) 2 A (Gp:) 4 A (avg) (Gp:) 100 W Boost, 100% efficiency
(Gp:) + (Gp:) – (Gp:) C (Gp:) D (Gp:) L (Gp:) S (Gp:) RL (Gp:) – (Gp:) + (Gp:) 50 V (Gp:) 25 V (Gp:) 2 A (Gp:) 4 A (avg) (Gp:) 100 W Buck-Boost, 100% efficiency
vS_max = vD_max = 75 V iS_avg = 4 A iD_avg = 2 A iL_avg = 6 A FOMVA_S = 300 VA FOMVA_D = 150 VA Higher electrical stress in the case of Buck-Boost converter Therefore, lower actual efficiency
Comparing basic DC/DC converters (VI) Price to pay for simultaneous step-down and step-up capability: Higher electrical stress on components and, therefore, lower actual efficiency
Converters with limited either step-down or step-up capability: Lower electrical stress on components and, therefore, higher actual efficiency
Comparing basic DC/DC converters (VII) (Gp:) 300 W Boost, 98% efficiency (Gp:) + (Gp:) – (Gp:) C (Gp:) L (Gp:) S (Gp:) D (Gp:) RL (Gp:) + (Gp:) – (Gp:) 60 V (Gp:) 50 V (Gp:) 5 A (Gp:) 6.12 A (avg) (Gp:) 1.12 A (avg)
Example of power conversion between similar voltage levels based on a Boost converter Very high efficiency can be achieved!!! vS_max = vD_max = 60 V iS_avg = 1.12 A iD_avg = 5 A iL_avg = 6.12 A FOMVA_S = 67.2 VA FOMVA_D = 300 VA
Comparing basic DC/DC converters (VIII) The opposite case: Example of power conversion between very different and variable voltage levels based on a Buck-Boost converter High efficiency cannot be achieved!!! (Gp:) 300 W Buck-Boost, 75% efficiency (Gp:) + (Gp:) – (Gp:) C (Gp:) D (Gp:) L (Gp:) S (Gp:) RL (Gp:) – (Gp:) + (Gp:) 60 V (Gp:) 20 – 200 V (Gp:) 5 A (Gp:) 20 – 2 A (avg)
vS_max = vD_max = 260 V iS_avg_max = 20 A iD_avg_max = 5 A iL_avg = 25 A FOMVA_S_max = 5200 VA FOMVA_D = 1300 VA Remember previous example: FOMVA_S = 67.2 VA FOMVA_D = 300 VA
Comparing basic DC/DC converters (IX) One disadvantage exhibited by the Boost converter: The input current has a “direct path” from the input voltage source to the load. No switch is placed in this path. As a consequence, two problems arise: Large peak input current in start-up No over current or short-circuit protection can be easily implemented (additional switch needed) Buck and Buck-Boost do not exhibit these problems (Gp:) + (Gp:) – (Gp:) C (Gp:) vg (Gp:) L (Gp:) S (Gp:) D (Gp:) RL (Gp:) vO (Gp:) + (Gp:) – (Gp:) Boost
Synchronous rectification (I) To use controlled transistors (MOSFETs) instead of diodes to achieve high efficiency in low output-voltage applications This is due to the fact that the voltage drop across the device can be lower if a transistor is used instead a diode The conduction takes place from source terminal to drain terminal In practice, the diode (Schottky) is not removed (Gp:) S (Gp:) L (Gp:) D
(Gp:) S1 (Gp:) L (Gp:) S2
(Gp:) S1 (Gp:) L (Gp:) S2
(Gp:) idevice (Gp:) vdevice (Gp:) Diode
(Gp:) MOSFET
Synchronous rectification (II) In converters without a transformer, the control circuitry must provide proper driving signals In converters with a transformer, the driving signals can be obtained from the transformer (self-driving synchronous rectification) Nowadays, very common technique with low output-voltage Buck converters (Gp:) S1 (Gp:) L (Gp:) S2 (Gp:) Feedback loop (Gp:) – (Gp:) Vref (Gp:) Av (Gp:) vO (Gp:) PWM (Gp:) Q (Gp:) Q’
(Gp:) RL (Gp:) vg (Gp:) vO (Gp:) C (Gp:) L (Gp:) + (Gp:) – (Gp:) + (Gp:) – (Gp:) Synchronous Buck (Gp:) S1 (Gp:) S2 (Gp:) D
Input current and current injected into the output RC cell (I) (Gp:) vg (Gp:) ig (Gp:) iD (Gp:) D (Gp:) vD (Gp:) + (Gp:) – (Gp:) S (Gp:) iS (Gp:) vS (Gp:) + (Gp:) – (Gp:) RL (Gp:) vO (Gp:) + (Gp:) – (Gp:) DC/DC converter (Gp:) + (Gp:) – (Gp:) C (Gp:) iRC
(Gp:) t (Gp:) Desired current (Gp:) ig
(Gp:) t (Gp:) iRC (Gp:) Desired current
If a DC/DC converter were an ideal DC transformer, the input and output currents should also be DC currents As a consequence, no pulsating current is desired in the input and output ports and even in the current injected into the RC output cell
Input current and current injected into the output RC cell (II) (Gp:) t (Gp:) ig (Gp:) Noisy (Gp:) RL (Gp:) vg (Gp:) vO (Gp:) S (Gp:) iRC (Gp:) ig (Gp:) C (Gp:) L (Gp:) D (Gp:) + (Gp:) – (Gp:) + (Gp:) – (Gp:) Buck (Gp:) t (Gp:) Low noise (Gp:) iRC
(Gp:) + (Gp:) – (Gp:) C (Gp:) vg (Gp:) L (Gp:) S (Gp:) D (Gp:) RL (Gp:) vO (Gp:) + (Gp:) – (Gp:) Boost (Gp:) ig (Gp:) iRC (Gp:) Low noise (Gp:) t (Gp:) ig (Gp:) t (Gp:) Noisy (Gp:) iRC
(Gp:) vO (Gp:) + (Gp:) – (Gp:) + (Gp:) – (Gp:) C (Gp:) D (Gp:) vg (Gp:) L (Gp:) S (Gp:) RL (Gp:) Buck-Boost (Gp:) ig (Gp:) iRC (Gp:) t (Gp:) Noisy (Gp:) ig (Gp:) t (Gp:) Noisy (Gp:) iRC
ESTA PRESENTACIÓN CONTIENE MAS DIAPOSITIVAS DISPONIBLES EN LA VERSIÓN DE DESCARGA